ECE 697 Delta-Sigma Data Converter Design
Spring 2010, Boise State University
Instructor : Vishal Saxena
Time : Tuesday and Thursday, 6:30 to 7:45 PM
Course dates : Tuesday, January 19 to Thursday, May 6
Location : MEC 106
Holidays : March 30 and April 1, Spring break.
Office : MEC 202 F
Office hours : Tue. & Thu., 5:00-6:30 pm
E-mail : vishalsaxena AT boisestate DOT edu
Lecture notes and accompanying material are here.
Assignments and projects can be found here.
MATLAB examples are posted here.
Course content – Data Conversion and spectral estimation fundamentals, Delta-Sigma modulator (DSM) architectures, decimation filters, discrete-time (switched-capacitor) as well continuous-time (CT) DSM design, Cascaded DSMs, Bandpass and Complex DSMs, Flash ADCs and DACs employed in the DSMs, DAC mismatch error shaping, effects of excess-loop delay and clock jitter in CT-DSMs, tuning techniques for CT-DSMs. Delta-Sigma DAC architectures.
Prerequisites – Background in Analog IC Design (ECE 511) and Digital Signal Processing. Basic knowledge of circuit simulation using Spice/Spectre and Matlab scripting.
Textbook – Understanding Delta-Sigma Converters – Richard Schreier and Gabor Temes, Wiley-IEEE Press, 2005.
The complete reference list for delta-sigma modulators is available here.
· Homeworks (25%): Weekly assignments incorporating Matlab as well as Spectre based design and simulation.
· Mid-Term Exam (25%)
· Project 1 (25%): Switched-capacitor delta-sigma modulator design.
· Project 2 (25%): Continuous-time delta-sigma modulator design.
Use of laptop in the class is encouraged for simulations while internet surfing is not.
Late work will not be accepted.
While collaboration in homeworks and projects is encouraged but blatantly copying stuff (plagiarism) is not allowed.