Neuromorphic and Cognitive Integrated Circuits

Our group is investigating bio-inspired cognitive systems-on-a-chip (SoCs) that will introduce a new paradigm for massively-parallel and event-driven computing platforms to transcend the limitations of traditional computing architecture in nano-scale CMOS technologies. We envision chips performing pattern recognition with complexity an order of magnitude higher than traditional computing and signal processing architectures, and at power levels orders of magnitude lower than in traditional von Neumann computers.

To realize neural-inspired computing, we are investigating circuit architectures for adaptive Machine Learning algorithms developed by the computational Neuroscience community. This is achieved by a large organization of mixed-signal circuit motifs comprised of event driven and energy efficient silicon neurons and a dense fabric of compact synapses integrated on CMOS chips. Our present research focus in this area includes:

  • Design of transistor-based synapses with small layout footprint, biologically compatible plasticity rules and dense-integration in a nano-CMOS process with power consumption in the pJ range.

  • Energy-efficient, compact neurons to drive dense synaptic arrays in nano-CMOS technologies for achieving neuron density greater >10^3 neurons on a single die.

  • We are investigating several challenges in emergent and supervised learning of spiking neural-networks, realizing higher-level cognition and translation of emerging neural-inspired machine learning algorithms into chip scale systems with minimum circuit area and power overhead.

  • Ultra low-power interconnects for event-driven (AER) communication in a large network of neuromorphic computing cores.
  • When successfully demonstrated, the proposed cognitive computing architectures will realize a massively parallel, highly scalable and energy-efficient event-driven intelligent signal processing (ISP) platform to tackle complex real-time machine learning tasks such as pattern recognition, robotic control, visual pattern and motion detection and brain-machine interfaces with power consumption comparable to biological brains.

    A test-chip with spiking neurons, fabricated in 180-nm CMOS, 2013.

    A Neuromorphic test chip with spiking neurons and backend resistive memory, fabricated in 180-nm CMOS, 2014.